FIG. 1 Prior Art—Traditional Transistors in Parallel Connection
FIG. 1 shows traditional transistors in parallel connection, the first transistor T1 with a first Gate G1; the dielectric layer 11 is made under the first gate G1. The dielectric layer 11 has two ends; a source S and a drain D are made under the dielectric layer 11, each near one of the two ends of the first dielectric layer 11. A second transistor T2 with a second Gate G2, is in parallel to and spaced apart from the first gate G1; a dielectric layer 12 is made under the second gate G2. The dielectric layer 12 has two ends; the common source S and the common drain D are extended under the dielectric layer 12, each near one of the two ends of the dielectric layer 12. There is semiconductor material 13 between the common source S and the common drain D.
The two transistors T1, T2 in parallel connection according to the traditional structure are with the same device structure, and having a similar threshold voltage (Vt). The two gates G1, and G2 are made of the same semiconductor material and doped with a same dopant. A unit length L exists between them to form two transistors in parallel connection. The minimum length in Y direction for the traditional transistors in parallel connection is of three unit lengths (3 L). A unit length L is a minimum width of a design rule used in the manufacturing process for such transistors.
Nowadays, a typical memory chip has 108˜1010 transistors made thereon in a single chip. With the technology progress, the number of transistor in a single chip is increasing progressively. As the number of transistor increases for a single chip, the semiconductor material used for a memory chip is therefore increasing. It is desirable to reduce the occupied chip area for a single memory chip on a piece of wafer, while with a same number of transistors on a single memory chip. This not only increases yield for a semiconductor wafer but also meets the requirement of light weight and miniaturization for a memory chip.
FIG. 2 Prior Art—Traditional Transistors in Series Connection
FIG. 2 shows traditional transistors in series connection, the first transistor T21 with a first Gate G21. A dielectric layer 21 is made under the first transistor T21. A source S is made under and on the left side of the dielectric layer 21. A drain/source DS is made under and on the right side of the dielectric layer 21. A second transistor T22 with a second Gate G22 is neighboring to the first transistor T21. A dielectric layer 22 is made under the second gate G22. The drain/source DS functions as a source for the second transistor T22. A drain D is made under and on the right side of the dielectric layer 22. There is semiconductor material 23 in between the drains D and the sources S. The first gate G21 and the second G22 are spaced by a unit length (L). A unit length L is a minimum width of a design rule used in the manufacturing process for such transistors.
The two transistors T21, T22 in series connection according to the traditional structure are with a same device structure, and having a similar threshold voltage (Vt). The two gates G21, G22 are made of the same semiconductor material and doped with a same dopant. A unit length L exists between them to form two transistors in series connection. The minimum distance in X direction is of five unit lengths (5 L). A unit length L is a minimum width of a design rule used in the manufacturing process for such transistors.